3.0    Hardware

The following image shows where some of the hardware components are located.

3.1    Microcontroller

The Eagle 100 includes a Luminary Micro Stellaris LM3S6918 microcontroller. This 32-bit ARM Cortex-M3 RISC microcontroller is capable of 50-MHz operation with a Thumb2 instruction set for smaller object code. It has hardware division and single cycle multiplication for fast calculations. The nested vector interrupt controller provides interrupt handling for 33 interrupts with eight levels of priority. Please see the Luminary Micros’ LM3S6918 Microcontroller Data Sheet for more information and register definitions.

LM3S6918 key features:

•    Internal Memory
    ▫ 256 kilo-bytes flash
    ▫ 2-kB flash block protection defined by the user
    ▫ Flash data programming
    ▫ User defined and managed flash-protection block
    ▫ 64 kilo-bytes SRAM
•    Timers
    ▫ Four General Purpose Timer Modules (GPTM)
        Each GPTM can operate independently
        Each module provides two 16-bit timers or one 32-bit timer
        Can be used for Pulse Width Modulation (PWM)
        Can be used to trigger analog to digital conversions
    ▫ System Timer (SysTick)
        24-bit clear on write decrementing counter
        Uses include RTOS tick timer, high speed alarm timer, or a simple counter
    ▫ ARM FIRM compliant Watchdog Timer
        32-bit decrementing counter
        Programmable load register
        Separate clock with an enable
•    10/100 Ethernet Controller
    ▫ IEEE 802.3-2002 specification
    ▫ Half and full duplex for 10 Mbps and 100 Mbps
    ▫ Automatic MDI/MDI-X cross over correction
    ▫ Programmable MAC address
    ▫ Power down and power saving modes
•    UART
    ▫ Two fully programmable 16C550 type UARTs
    ▫ Separate transmit and receive FIFOs
    ▫ Baud rates up to 3.125 Mbps
    ▫ Loopback mode for testing and debugging
•    Synchronous Serial Interface (SSI)
    ▫ Master or slave operation
    ▫ Separate transmit and receive FIFOs
    ▫ Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces
    ▫ Internal loopback mode for testing and debugging
•    I2C Module
    ▫ Master or slave operation
    ▫ 100 kbps or 400 kbps transmission speed
    ▫ Mulitmaster support
    ▫ 7-bit addressing mode
•    Analog-to-Digital Converter
    ▫ Eight 10-bit channels
    ▫ Single and differential input configurations
    ▫ 500k samples per second
    ▫ Four programmable sampling sequences with conversion result FIFOs
    ▫ Sequences triggered by software, timers, analog comparators, or GPIO
    ▫ On-chip temperature sensor
•    General Purpose Input or Outputs (GPIO)
    ▫ 5V tolerant inputs
    ▫ Every GPIO is capable of edge triggered or level sensitive interrupts
    ▫ Enable or disable internal weak pull-up or pull-down resistors
    ▫ Programmable open drain input or outputs
    ▫ Programmable drive current of 2mA, 4mA, or 8mA
•    Reset Sources
    ▫ Power on reset
    ▫ Reset pin assertion
    ▫ Brown out reset
    ▫ Software reset
    ▫ Watchdog timer reset
•    Additional Features
    ▫ IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
    ▫ Debugging via JTAG or Serial Wire interfaces
    ▫ Programmable PLL for system clock

3.2    CPLD

A Xilinx’s XC9572XL Complex Programmable Logic Device(CPLD) comes standard on the Eagle 100. The CPLD supports in-system programming via an IEEE 1149.1 boundary-scan JTAG. The XC9572XL is a 3.3V CPLD with 5V tolerant pins. The CPLD has 1,600 usable gates and 72 macrocells. For further information please see Xilinx’s XC9500XL High-Performance CPLD Family Data Sheet.

3.3    DAC

The Eagle 100 includes a National Semiconductor’s DAC104S085 general purpose digital-to-analog converter (DAC). The DAC has four channels with a resolution of 10-bit. The output amplifiers allow for a rail-to-rail output swing from 0 to 3.3V. Communication to the DAC is done through a three wire synchronous serial interface that operates up to 40 MHz. The DAC’s outputs have a settling time of 6µs. It allows for simultaneous output updating. For further information please see National Semiconductor’s DAC104S085 Data Sheet.

Revised: August, 2008